LU-3676 llite: to configure max_cached_mb correctly

If there exists MGS conf_param to reduce the memory cache
max_cached_mb it will fail because dt_exp is not initialized
yet.

It should just go ahead and configure it because certainly it
have enough free LRU slot to deduct ccc_lru_left.

Signed-off-by: Jinshan Xiong <jinshan.xiong@intel.com>
Change-Id: I317e556413bc63086378dec294d8ba2792afca52
Reviewed-on: http://review.whamcloud.com/11783
Tested-by: Jenkins
Tested-by: Maloo <hpdd-maloo@intel.com>
Reviewed-by: Bobi Jam <bobijam@gmail.com>
Reviewed-by: Andreas Dilger <andreas.dilger@intel.com>

diff --git a/lustre/llite/lproc_llite.c b/lustre/llite/lproc_llite.c
index d4dcece..112e8f9 100644 (file)
--- a/lustre/llite/lproc_llite.c
+++ b/lustre/llite/lproc_llite.c
@@ -436,9 +436,6 @@ ll_max_cached_mb_seq_write(struct file *file, const char __user *buffer,
                RETURN(-ERANGE);
        }
 
-       if (sbi->ll_dt_exp == NULL) /* being initialized */
-               GOTO(out, rc = 0);
-
        spin_lock(&sbi->ll_lock);
        diff = pages_number - cache->ccc_lru_max;
        spin_unlock(&sbi->ll_lock);
@@ -477,6 +474,11 @@ ll_max_cached_mb_seq_write(struct file *file, const char __user *buffer,
                if (diff <= 0)
                        break;
 
+               if (sbi->ll_dt_exp == NULL) { /* being initialized */
+                       rc = -ENODEV;
+                       break;
+               }
+
                /* difficult - have to ask OSCs to drop LRU slots. */
                tmp = diff << 1;
                rc = obd_set_info_async(env, sbi->ll_dt_exp,