LU-241 Support crc32c with hardware accelerated instruction as one of lustre checksums

LU-241 Support crc32c with hardware accelerated instruction as one of lustre checksums

Adding CRC32C as new lustre checksum algorithm. Because of crc32c,
the Intel Nehalem based CPU supports h/w accelerated crc32c
instruction as one of SSE4.2 instruction set. The new crc32c codes
in the lustre also use this h/w instruction. The lustre also
automatically detects whether crc32c instruction is available, if
not, use adler (fastest checksum other than crc32c).

Change-Id: I764851a46a94a879239cd127eac411e98342e67f
Signed-off-by: Shuichi Ihara <sihara@ddn.com>
Reviewed-on: http://review.whamcloud.com/1009
Tested-by: Hudson
Reviewed-by: Andreas Dilger <adilger@whamcloud.com>
Tested-by: Maloo <whamcloud.maloo@gmail.com>
Reviewed-by: Johann Lombardi <johann@whamcloud.com>
Reviewed-by: Oleg Drokin <green@whamcloud.com>